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xuliejianceqi
- 序列检测器在数据通信、雷达和遥控领域中用于检测同步识别标志。他是一种用来检测一组或多组序列型号的电路-Sequence detector in data communication, radar and remote areas to detect synchronization marker. He is used to detect one or more types of circuit sequence
exp_10100101
- 序列检测器的基本例题，源代码哦，希望给大家带来帮助-Sequence detector basic examples, source code Well, I hope to bring to help you
PAM
- 该程序完成一个16电平PAM数字通信系统的仿真，并测量了它的误码率。首先产生信息符号序列，该序列被当做4个信息比特一组，将16组符号映射到16个信息幅度。检测器计算距离，输出与真正传输的信息符号序列作比较，然后将差错计数。- This procedure completes a 16 level PAM digital communication system s simulation, and has surveyed its error rate. First has the message
Tutorial_5
- 一个序列检测器的FPGA设计实验，通过LED灯显示，基于Spartan-3e开发板-The sequence detector will look for the input series “10010.” LED’s will show how much of the series has been detected and when the entire series has been entered an additional LED will come on. Circuit input
PROGRAM
- PROGRAM FOR SEQUENCE DETECTOR
vhdlcoder
- 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。 二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可
VHDL
- 序列检测器设计VHDL源程序 任意输入串行数据串-VHDL source code sequence detector design arbitrary string of serial data input
ram
- vhdl program for random access memory and sequence detector
vhdl
- 检测一组或多组又二进制码组成的脉冲序列信号，当序列检测器连续收到一组或多组序列信号，如果与预先设置的码相同的时候，输出1，否则输出0. -Detection of one or more group was composed of binary code pulse train signal, when the sequence detector continuous sequence of one or more groups received signal, if the same co
serial_check
- 本实验需要实现一个序列检测器，用来检测输入的串行位流是否和程序设定的位串相一致，若一致则在验证波形的出现一个高电位来表示。本实验需要验证的位串是“101011”。-In this study, need to implement a sequence detector, to detect whether the input serial bit stream and procedures consistent set of bit strings, if the same occurs in
sequence_detector
- verilog progam on sequence detector
Seqcheck
- 用VHDL编写的序列检测器，是完整工程。-Written by VHDL sequence detector is a complete project.
text
- 序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号。本系统用状态机来实现序列（1110010）的序列检测器的设计，若系统检测到串行序列 1110010 则输出为 1 ,否则输出为 0 ，并对其进行波形和功能仿真。-Sequence detection can be used to detect one or more groups formed by the binary code pulse train signal. The system implemented by the st
alu_sequence_detector_1101
- It is verilog based implementation of ALU and sequence detector for detecting sequence 1101
ztj
- 摩尔状态机检验程序，序列检测器，1100101检测-Moore state machine testing procedures, the sequence detector, 1100101 test
seqbet
- 10011序列检测器，verilog语言编写的检测器-10011 sequence detector
state
- 实现的是序列检测器，给出输入序列，并进行检验，如果满足连续为110011101则输出为1-To achieve the sequence detector, given the input sequence, and tested, if the continuous output of 1 to 110,011,101
spuc2.3.1
- Readme Complex class is very similar to the Standard C++ library complex class and the standard C++ class could be substituted in many cases. Code is wrapped in namespace SPUC SPUC DSP C++ source code library directory structure array -
seqdet
- 用VERILOG 语言进行的序列检测器设计，初学者多用于练习。-Sequence detector design
VHDL_design
- 以VHDL设计一有限状态机构成的序列检测器。序列检测器是用来检测一组或多组序列信号的电路，要求当检测器连续收到一组串行码（如1110010）后，输出为1，否则输出为0。-With VHDL Design into a finite state machine sequence detector. Sequence detector is used to detect the signal sequence of one or more groups of circuits, require th